1. Field
This disclosure relates generally to an electronic assembly and, more specifically, to techniques for reducing inductance in through-die vias of an electronic assembly.
2. Related Art
Various approaches have been utilized or proposed for building three-dimensional (3D) integrated circuits (ICs). As one example, 3D ICs may be built using a monolithic approach, where electronic components and their connections are built in layers on a single semiconductor wafer that is diced into multiple 3D ICs. In this case, as there is only one die, there is no need for aligning, thinning, or bonding multiple die, or implementing through-silicon vias (TSVs). As is known, a TSV is a vertical electrical connection that passes completely through a silicon wafer or die and may optionally extend through layers of devices and interconnects formed on a surface of the silicon wafer or die. As another example, 3D ICs may be built using a wafer-on-wafer approach, where electronic components are built on two or more semiconductor wafers that are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are usually either built into the stacked wafers before bonding or are created in the wafer stack after bonding. For example, in the wafer-on-wafer approach, TSVs may be implemented that pass through a silicon substrate or substrates between active layers and/or between an active layer and an external bond pad.
As another example, a 3D IC may be built using a die-on-wafer approach, where electronic components are built on two semiconductor wafers. A first wafer is then diced and the singulated die are aligned and bonded onto die sites of a second wafer. As in the wafer-on-wafer approach, thinning and TSV creation may be performed either before or after bonding. Additional die may be added to the die-on-wafer stacks before dicing. As another example, a 3D IC may be built using a die-on-die approach, where electronic components are built in multiple die, which are then aligned and bonded. In the die-on-die approach, thinning and TSV creation may be done before or after bonding. One advantage of the die-on-die approach is that each component die can be tested before insertion into a die-on-die stack, such that one non-functional die does not ruin an entire die-on-die stack. Moreover, each die that is to be utilized in a die-on-die stack can be binned, so that the die can be mixed and matched to optimize power consumption and performance (e.g., matching multiple die from a low power process corner for a mobile application).
As yet another example, a 3D IC may be built using a package-on-package (PoP) approach, which is an IC packaging technique that combines vertically discrete logic and memory ball grid array (BGA) packages. Two or more packages are stacked and a standard interface is usually employed to route signals between the packages. The PoP approach facilitates relatively high component density and has been employed in various portable electronic devices, e.g., mobile phones, personal digital assistants (PDAs), and digital cameras. Known PoP configurations have utilized pure memory stacking (with two or more memory only packages stacked on each other) and mixed logic-memory stacking (where a memory package is stacked on one side of a logic (central processing unit (CPU)) package, i.e., opposite a motherboard.